The purpose of this thesis is to describe the channel coding algorithms used
in the TETRA-system and to study the implementation of these algorithms
using a digital signal processor (DSP). The focus is on block and
convolutional codes.First, the basics of wireless communication systems are
reviewed including different access methods. Also the properties of the
mobile communication channel including fading are examined with respect to
the TETRA-system. Then, the TETRA-system and the used DSP are presented. The
basic principles of channel coding and the channel coding algorithms used in
the TETRA-system are described.Efficient computation of the TETRA shortened
cyclic block code used also in the CCITT s Recommendation X.25 is studied.
Algorithms are presented for the DSP implementation of the block code using
a table access and a shift register. Various representation methods of
convolutional codes, including the shift register structure, the tree
diagram, the trellis diagram, and the state diagram, are illustrated using
the mother code of TETRA. In TETRA the convolutional coding consists of
mother encoding and puncturing. The puncturing methods used are described,
and in the implementation the focus is on RCPC 2/3 code (Rate-Compatible
Punctured Convolutional code of rate 2/3). After studying the encoding,
decoding by the Viterbi-algorithm is studied. Other channel coding
algorithms used in the TETRA system are also described shortly, including
interleaving, scrambling, and Reed-Muller code.The results achieved show
that the computationally demanding TETRA channel decoding can be done fast
enough using DSP when efficient algorithms are used. In fact, in addition to
error control functions, computational capacity is available also for other
receiver algorithms.
Keywords: channel coding, convolutional coding, block coding, DSP, TETRA
Updated 4.1.1996 by
anne.saarinen@hut.fi